1. Field of the Invention
The invention relates to a decoder in a semiconductor memory device such as FIFO (First-In First-Out) memory or serial register in which addresses cannot be accessed at random and only a serial access can be executed and memory cells of a dynamic type are used and, more particularly, to a testing circuit of redundant memory cells.
2. Description of Related Art
Hitherto, as a redundancy circuit to rescue a defective memory cell in a semiconductor memory device, for example, a redundancy circuit is disclosed in Japanese Patent Kokai No. 6-203590 (patent document 1).
In the patent document 1, in a nonvolatile semiconductor memory device of an electrically batch erasing type such as random access flash memory (for example, EPROM which can be erased by ultraviolet rays and is electrically writable), a technique regarding a word line redundancy circuit on the row side has been disclosed.
In a semiconductor memory device using a dynamic type memory cell using a storing function by storage of charges due to a capacitance of a gate of an MOS transistor and a high input resistance, methods of rescuing a defective memory cell by preparing a redundant memory cell have widely been put into practical use. Particularly, as one of the methods of rescuing the defective memory cell in the column direction, what is called a shift type redundancy circuit in which memory cells after the defective memory cell are sequentially shifted is used. An example of a construction of a semiconductor memory device having the shift type redundancy circuit is shown in FIG. 1.
FIG. 1 is a constructional diagram showing an outline of the conventional semiconductor memory device.
The semiconductor memory device has the shift type redundancy circuit, is a memory such as an FIFO memory in which an address cannot be set and only a serial access can be performed, and has a memory cell array 1 for storing data. The memory cell array 1 has: a plurality of word lines WL of the row direction; a plurality of pairs of bit lines BL and opposite-phase bit lines BLb which perpendicularly cross the plurality of word lines WL; and a plurality of pairs of transfer data lines DL and opposite-phase transfer data lines DLb which are arranged in parallel with the pairs of bit lines BL and BLb and electrically connected. Dynamic type memory cells 2 are connected to crossing points of each word line WL and the bit lines BL and BLb, respectively, and arranged in a matrix shape. Each of the dynamic type memory cells 2 is a memory cell of one-transistor type constructed by: a capacitor 2a for accumulating charges connected to a power line; and an n-channel type MOS transistor (hereinafter, abbreviated to “NMOS”) 2b for transferring the charges connected between the capacitor 2a and the bit line BL or BLb. A gate of the NMOS 2b is connected to the word line WL and its drain is connected to the bit line BL or BLb.
A plurality of word lines WL are connected to a row decoder section 3 for decoding row addresses and selectively activated by outputs of the row decoder section 3. A sense amplifying section 4-1 is connected to one end side of the plurality of pairs of bit lines BL and BLb and a sense amplifying section 4-2 is also connected to the other end side of the pairs of bit lines BL and BLb. The sense amplifying section 4-1 has a plurality of sense amplifiers 5A connected between the bit lines BL and BLb. Similarly, the sense amplifying section 4-2 has a plurality of sense amplifiers 5B connected between the bit lines BL and BLb. Each of the sense amplifiers 5A and 5B is a circuit for amplifying an electric potential difference between the bit lines BL and BLb upon reading the data.
A read register section 6-1 is connected to one end side of the plurality of pairs of transfer data lines DL and DLb connected to the pairs of bit lines BL and BLb. A write register section 6-2 is connected to the other end side of the pairs of transfer data lines DL and DLb. The read register section 6-1 has a plurality of read registers 7A connected between the transfer data lines DL and DLb. Each read register 7A is a circuit for receiving read data read out from the pair of bit lines BL and BLb through the pair of transfer data lines DL and DLb and temporarily holding it. Each write register 7B is a circuit for temporarily holding write data into the memory cell 2 and sending the holding write data to the bit lines BL and BLb through the transfer data lines DL and DLb.
A pair of read data lines RDL are connected to one end side of each pair of transfer data lines DL and DLb through each pair of NMOSs 8A-1 and 8A-2 for transferring the data. A common gate of each pair of NMOSs 8A-1 and 8A-2 is connected to a column decoder section 9-1 for reading through a column line CL. The column decoder section 9-1 decodes a column address for reading, controls ON/OFF of the plurality of pairs of NMOSs 8A-1 and 8A-2, and connects one end side of the pair of transfer data lines DL and DLb and the read data lines RDL. The column decoder section 9-1 is constructed by a plurality of decoders 10A. A pair of write data lines WDL are connected to the other end side of each pair of transfer data lines DL and DLb through each pair of NMOSs 8B-1 and 8B-2 for transferring the data. A common gate of each pair of NMOSs 8B-1 and 8B-2 is connected to a column decoder section 9-2 for writing through the column line CL. The column decoder section 9-2 decodes a column address for writing, controls ON/OFF of the plurality of pairs of NMOSs 8B-1 and 8B-2, and connects the other end side of the pair of transfer data lines DL and DLb and the write data lines WDL. The column decoder section 9-2 is constructed by a plurality of decoders 10B. Each of the decoders 10A and 10B is constructed by the same circuit although their column addresses which are inputted are different.
In the memory cell array 1 shown in FIG. 1, for example, a plurality of groups of memory cell 2 connected to the plurality of bit lines BL and BLb in the upper portion construct a normal cell section (ordinary cell section) 11 and a plurality of groups of memory cell 2s connected to the bit lines BL and BLb in the lowest portion construct a redundant cell section 12. As for the redundant cell section 12, to rescue the defective memory cell 2 in the normal cell section 11, when the defective memory cell 2 becomes a target for reading or writing (accessing) the data, the redundant cell section 12, the redundant memory cell 2s is accessed in place of the defective memory cell 2.
In the semiconductor memory device in FIG. 1, when data DA is written into the memory cell 2 connected to a certain word line WL and a certain bit line BL, the supplied row address AX and column address AY are decoded by the row decoder section 3 and the column decoder section 9-2 for writing. The word line WL is activated to the “H” level and, at the same time, the NMOSs 8B-1 and 8B-2 in the column address AY are turned on. The write data DA inputted to the write data lines WDL is transferred to the transfer data lines DL and DLb connected thereto through the NMOSs 8B-1 and 8B-2 in the ON state and held in the register 7B connected thereto. The data DA held in the register 7B is sent through the transfer data lines DL and DLb to the bit lines BL and BLb connected thereto and stored into the capacitor 2a through the NMOS 2b in the memory cell 2 in the ON state by the word line WL at the “H” level.
For example, if there previously is a defect in the memory cell 2 and the defective memory cell 2 has been replaced by the redundant memory cell 2s, when the row address AX and the column address AY are supplied, they are decoded by the row decoder section 3 and the column decoder section 9-2 for writing, the redundant memory cell 2s is selected in place of the defective memory cell 2, and the data DA is written into the redundant memory cell 2s. 
In the case of reading out the data DA stored in the memory cell 2, the supplied row address AX is decoded by the row decoder section 3, the word line WL is activated to the “H” level, and each NMOS 2b in the plurality of memory cells 2 connected thereto are turned on. When each NMOS 2b in the plurality of memory cells 2 is turned on, the data DA stored in each capacitor 2a is read out to each pair of bit lines BL and BLb, amplified by each sense amplifier 5A connected thereto, and thereafter, held in each register 7A. The supplied column address AY for reading is decoded by the column decoder section 9-1 for reading and only the NMOSs 8A-1 and 8A-2 in the column address AY are turned on. The data held in the register 7A is read out to the read data lines RDLs through the transfer data lines DL and DLb and the NMOSs 8A-1 and 8A-2 in the ON state.
For example, if there previously is a defect in the memory cell 2 and the defective memory cell 2 has been replaced by the redundant memory cell 2s, the data DA which is stored in the defective memory cell 2 is stored in the redundant memory cell 2s in place of the defective memory cell 2. When the row address AX and the column address AY are supplied in order to read out the data, therefore, they are decoded by the row decoder section 3 and the column decoder section 9-1 for reading, the redundant memory cell 2s is selected in place of the defective memory cell 2, and the data DA is read out from the redundant memory cell 2s. 
In this type of semiconductor memory device, as a method of improving a rescue ratio of the defective memory cell 2, a redundant cell test to discriminate whether or not the defective memory cell 2s exists among a plurality of redundant memory cell 2s is often executed at the time of a probing test upon manufacturing. If the defective memory cell 2s exists among the redundant memory cells 2s, a program is made so as not to use the defective memory cell 2s. 
To execute the redundant cell test, the operating mode is set into a mode in which the redundant memory cell 2s is certainly selected by a test terminal (not shown) or the like and its address is designated, so that the presence or absence of a defect of the redundant memory cell 2s can be discriminated.